1. Field
This disclosure relates generally to data processing systems, and more specifically, to in-circuit tracing techniques suitable for on-chip interconnect fabrics.
2. Related Art
Increasingly complex on-chip interconnect micro-architectures have been developed, in part, to achieve higher data transfer bandwidths and/or lower latencies in system on a chip (SoC) designs. Typically, interconnect fabrics in accord with such micro-architectures seek to provide multi-path, point-to-point communications between a large and scalable set of processor cores, memory controllers, caches, direct memory access (DMA) controllers, bridges, etc. In some implementations, coherency management techniques are employed to present a coherent system memory state while allowing multiple in-flight interconnect transactions to proceed concurrently in accordance with some appropriate total ordering of transactions. Basic storage operations such as reading or writing of storage locations, synchronization, etc. may be implemented using multiple transactions between two or more end-point devices.
In these complex interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, it is becoming more and more challenging to efficiently trace and provide an external debugger with visibility into the data flow of the on-chip interconnect transactions. Some of these tracing challenges derive, at least in part, from the confluence of split-transaction techniques and the multiplicity of available interconnect paths and in-flight transactions.
Improved techniques are desired.
The use of the same reference symbols in different drawings indicates similar or identical items. Elements in the drawings are depicted with a goal of simplicity and clarity of illustration and have not necessarily been drawn to scale.